1. Field of the Invention
The present invention relates to three-dimensional (3-D) integrated circuits, and in particular to providing interlayer conductors to multiple planes of circuits in the devices.
2. Description of Related Art
3-D integrated circuits include multiple active layers in which conductive or semiconductive elements are disposed. 3-D memory integrated circuits include stacks of two-dimensional arrays of memory cells. Active layers in the stacks can include bit lines or word lines for example, which must be connected to peripheral circuits like decoders, sense amplifiers and the like. In some arrangements, the connections are made using interlayer conductors that extend from each active layer to a routing layer, such as a patterned metal layer that overlies the stacks of two-dimensional arrays. The patterned metal layer can be used to route signals and bias voltages between the arrays and the appropriate peripheral circuits. Similar signal routing structures can be used on other types of 3-D integrated circuits.
The interlayer conductors have lengths that vary in dependence on the active layer to which contact is made. Because of the varying lengths and other factors, techniques used to implement the interlayer conductors can involve multiple steps and require special processes. A variety of technologies that can be deployed for this purpose is described in co-pending and commonly owned patent applications, including U.S. patent application Ser. Nos. 13/049,303; 13/114,931; 13/240,058; 13/735,922; 13/736,104, each of which is incorporated by reference as if fully set forth herein.
As the number of active layers increases, some of the processes involved in formation of interlayer conductors can become more difficult. It is desirable, therefore, to provide technologies that support the formation of patterned conductors and interlayer conductors in 3-D integrated circuits as the number of active layers increases.